The present invention relates to improved performance amplifiers. More particularly, the present invention relates to methods for improving performance of differential amplifiers.
Most current receiving circuits are typically differential amplifiers or sense amplifier types. These circuits accept differential input signals and output differential output signals. Typically, such circuits take differential input voltage signals and covert the voltage to differential currents. These currents are typically integrated with capacitors coupled to the outputs of the differential amplifier. Accordingly, the delay of the circuit is a function of the differential current (the strength of the drivers) and the amount of capacitance in the capacitors.
When a differential receiver has an offset, for example, biased towards rising transitions or falling transitions, the differential currents will be larger for one transition or the other. Accordingly, the amount of delay from when the differential input signals transition to when the differential output signals transition will be different for the rising transition and for the falling transition. In other words, the variation in a rising transition delay and a falling transition delay will be different.
It has been discovered by the inventor that semiconductor process and manufacturing variations have a significant effect on differential amplifier performance. As an example, differential amplifiers may have a bias towards one state over another state, for example, a high bias or a low bias; and differential driver outputs of such amplifiers may have higher or lower output current relative to other amplifiers on the device. These variations cause differential amplifiers to have highly unpredictable behaviors from chip to chip or system to system. Such variations in behavior degrade the performance of the chips, systems, or the like.
In light of above, the inventor has determined that it is desirable to develop methods and apparatus that address the above problems.
The present invention relates to methods and apparatus for enhanced performance differential amplifiers. More particularly, the present invention relates to methods for configuring differential amplifiers to reduce inherent offsets.
Embodiments of the present invention, reduce delay variability of a differential amplifier by adjusting capacitance values at the output nodes. In one example, when the inherent offset biases the rising transition, then output capacitance is reduced. Thus, although the falling transition has a smaller differential current, the reduced output capacitance for the transition results in the same or similar amount of delay as the rising transition.
One embodiment includes outputs of a differential amplifier being coupled to an array of capacitors via controllable switches. Upon startup or calibration, the capacitors are iteratively switched in and out and the rising transition delay and falling transition delay of the differential amplifier are determined. The capacitor (s) that are used in the normal operation of the differential amplifier is the one that minimizes the variation in the rising transition delay and falling transition delay (delay variability).
According to one aspect of the invention, a method for reducing delay variability in a differential receiver is disclosed. One such technique includes receiving a plurality of differential input signals, and determining a first transition delay time of an output in response to the plurality of differential input signals. A technique may also include determining a second transition delay time of the output in response to the plurality of differential input signals, and modifying capacitance coupled to the output in response to the first transition delay time and to the second transition delay time.
According to another aspect of the invention, another method for configuring a differential amplifier is disclosed. A process may include varying an amount of capacitance coupled to the differential amplifier, and for each amount of capacitance coupled to the differential amplifier, determining an associated delay variability factor of the differential amplifier. Various processes may also include the steps of determining a target amount of capacitance, the target amount of capacitance having an associated delay variability factor lower than other associated delay variability factors, and coupling the target amount of capacitance to the differential amplifier.
According to yet another aspect of the invention, an apparatus for amplifying differential signals is disclosed. One system includes a differential amplifier having differential outputs, a series of controllable switches coupled to the differential outputs of the differential amplifier, and a series of capacitors coupled to the series of controllable switches. One additional embodiment may include a state machine coupled to the differential outputs and to the series of controllable switches, the state machine configured to vary an amount of capacitance coupled to the differential outputs by controlling the controllable switches, wherein the state machine is also configured to determine an associated delay variability factor of the differential amplifier for each capacitance coupled to the differential outputs, and wherein the state machine is configured to determine a target amount of capacitance, the target amount of capacitance having an associated delay variability factor lower than other associated delay variability factors.